The present invention relates to a technology of verifying logic functions created by a hardware description language such as Verilog HDL (Hardware Description Language), and particularly to a logic verification apparatus capable of preventing, when an indeterminate value is generated, the indeterminate value from being unintentionally erased, and identifying the source thereof.
In recent years, with semiconductor integrated circuits being equipped with many, high-performance functions, there arise needs for designing large-scale logic circuits in a short period. Additionally, HDL is receiving attention for reasons such that logic synthesis tools have reached a level for practical use, or prices of work stations and personal computers are decreasing while functions thereof are being enhanced.
Specifically, Verilog HDL, a grammar system based on C language, is being actively used among HDLs for reasons such as simplified description or abundant ability of describing a simulation. As a technology relating to Verilog HDL, there is an invention disclosed in Japanese Patent Laid-Open No. 2003-316840.
The invention disclosed in Japanese Patent Laid-Open No. 2003-316840 aims to perform only logic verification of design data described in the logic description language and eliminate the necessity of verifying the design data described in the net list by treating similarly the indeterminate value for the design data described in the logic description language and the design data described in the net list. The program causes a computer to execute an input procedure of inputting logic circuit design data described in the logic description language and a modification procedure of checking whether or not the signal in the logic circuit design data is an indeterminate value and, if it is an indeterminate value, changing the logic circuit design data so that the signal is propagated as an indeterminate value to a later stage of the logic circuit.
When branching of the signal is described in Verilog HDL, for example, the output value after the branching may be a determinate value even if the input value to the branching point is an indeterminate value (also denoted as X, hereinafter). In other words, it happens that X is erased for some cause. Accordingly, there may be a case that the user overlooks an “unintentional indeterminate value” generated in the circuit even if logic verification has been performed.
Particularly, it often happens that indeterminate values are not considered in logic synthesis performed after logic verification. That is, indeterminate values are treated as “Don't Care”, and determined to be either “0” or “1” as the result of synthesis. Therefore, it is necessary to sufficiently confirm that an indeterminate value does not affect the specification of the circuit when performing an RTL (Register Transfer Level) simulation.
However, there has been a problem that, because X happens to be erased in the circuit as described above, the user overlooks generation of an “abnormal indeterminate value not treated as Don't Care” and failure is detected in or after the net list generated by logic synthesis, and thereby the logic verification must be executed again.
Additionally with the RTL design, an indeterminate value is often assigned to a branching that does not affect the circuit specification such as a branching that will not be selected, for example. In logic synthesis, it often happens that an indeterminate value is treated as “Don't Care” and assigned to one of the circuits outputting “0” or “1” that is more advantageous in terms of area.
Although “Don't Care” branching must not be essentially selected in an RTL simulation, it happens to be selected for some cause. It is not rare that X is erased in a branching statement of Verilog HDL and the user overlooks generation of an indeterminate value as described above. It also happens that an indeterminate value is generated not only in the X created by an RTL code but also in a register that has not been initialized, and therefore the user has to confirm that the indeterminate value has been properly processed and erased.
Such problems cannot be solved by using the invention disclosed in Japanese Patent Laid-Open No. 2003-316840.
The present invention has been made to solve the above problems and aims to provide a logic verification apparatus capable of preventing, when an indeterminate value generated in logic verification, the indeterminate value from being unintentionally erased.